1. TSMC NVHBM base dies: what Nvidia is reportedly asking for
Nvidia is reportedly directing the three major memory makers, Samsung Electronics, SK Hynix and Micron, to manufacture the base dies of its custom NVHBM memory stacks on TSMC's 3-nanometer process. The report, dated October 18, 2026, describes an effort to give the most important logic layer of Nvidia's AI memory a single foundry supplier. Details come from industry reporting and have not been confirmed in statements from the companies named.
If the arrangement holds, it would mean that memory chips sold to the world's leading AI accelerator maker sit on logic built by one manufacturer regardless of which company made the DRAM. This article explains what NVHBM is, why the base die matters, how each memory maker is reportedly responding and what could change in the AI hardware supply chain.
2. What is NVHBM?
NVHBM is Nvidia's custom approach to high-bandwidth memory, announced in August 2026. High-bandwidth memory, usually shortened to HBM, stacks several DRAM chips vertically on top of a base die and connects them to a processor over a very wide interface. It is a core component of modern AI accelerators, because training and running large models requires moving huge volumes of data quickly.
The goal of NVHBM is to standardize how custom HBM is built, rather than letting each memory supplier choose its own approach. Its central design change is to move Nvidia's memory controller into the base die. The controller directs traffic between the memory and the processor, and it has traditionally been placed on the processor itself.
Nvidia states that the design can deliver up to 30 percent more memory bandwidth and 15 percent lower power consumption than standard HBM4E. These are design targets rather than measured results from shipping products, and they will only be proven once systems reach customers.
3. Why does the base die matter?
The base die is the bottom layer of an HBM stack. It handles communication between the DRAM layers above it and the processor beside it. In earlier generations, the base die was a relatively simple component that memory makers produced themselves. As the demands of AI hardware grow, it increasingly needs to contain more complex logic, which in turn requires leading-edge manufacturing.
Moving the memory controller into the base die also frees area on the GPU compute die. That space can be used for other purposes, which gives Nvidia more room to improve the processor. In effect, the company is shifting a function from its own chip to the memory stack and asking suppliers to build it to a common specification.
Standardization has a second purpose: verification. When three suppliers build the critical layer differently, each design must be tested separately, and differences can introduce risk. Using one process and one foundry is intended to make qualification more reliable across all three memory makers.
4. How are the three memory makers responding?
Micron has reportedly planned to use TSMC for its HBM4E base dies, including those for NVHBM. The company has said its HBM4E base die uses a foundry process, and trade reports identify that foundry as TSMC. Micron anticipates volume production in 2027 and expects the shift to improve profitability.
SK Hynix has a longer relationship with TSMC on this front. It previously used TSMC's 12-nanometer process for HBM4 base dies and is now reported to be prioritizing the 3-nanometer process for future HBM products, including custom versions.
Samsung is reported to have agreed to use TSMC's technology for NVHBM base dies, but it plans to keep some in-house capacity for standard HBM and other custom memory products. Samsung also operates its own foundry business, so the choice involves its competitive position as well as technical needs. Its approach has been described as a dual track in which base dies come from either its own foundry or TSMC, depending on the customer.
5. A division of labor between memory makers and foundries
Memory companies have traditionally handled production from start to finish. The NVHBM plan reflects a wider shift in which Samsung, SK Hynix and Micron hand base die production to TSMC. Memory makers concentrate on DRAM, the area in which they hold deep expertise, while foundries make the advanced logic layers beneath.
This split follows from the economics of manufacturing. Leading-edge logic processes cost a great deal to develop and operate, and TSMC has built its business around them. A DRAM maker that wanted to produce comparable logic in-house would need to invest heavily for a small component. Outsourcing lets each company focus on what it does best.
The arrangement also means the three suppliers become somewhat more alike on one layer of the product, which makes differences in DRAM quality, yield and delivery the main basis for competition.
6. Why memory has become a bottleneck for AI
Modern AI accelerators can perform calculations faster than memory can supply them with data, so overall performance is often limited by memory bandwidth rather than raw compute. That is why HBM has become one of the most sought-after components in the industry, and why the companies that make it have seen demand rise alongside accelerator sales.
Each new generation of HBM adds capacity and speed, but it also adds complexity. Stacking DRAM chips, connecting them through thousands of tiny vertical links and managing heat in the stack all demand precise manufacturing. Any change to the base die affects how the whole stack is assembled, tested and cooled, which is why a decision on which foundry builds it carries weight far beyond one component.
Power is a particular concern. Large AI data centers are constrained by electricity supply, so a 15 percent reduction in memory power, if achieved, would let operators run more hardware within the same limits. Bandwidth gains work in the same direction by allowing each accelerator to do more useful work.
7. What a 3-nanometer process offers
A manufacturing node such as 3 nanometers describes a generation of chip fabrication technology. Newer nodes generally pack more transistors into the same area and use less energy per operation than older ones. Earlier HBM base dies, which were relatively simple, could be built on mature and inexpensive processes. Placing a memory controller into the base die raises the logic requirements and makes a more advanced process attractive.
The reported move to 3 nanometers therefore fits the trend of base dies taking on functions that used to belong to the processor. It also explains why memory makers, whose own fabrication lines focus on DRAM, would turn to a foundry that specializes in logic.
Because the details come from trade reporting, the specific nodes can differ between sources. One account describes SK Hynix using a 12-nanometer process for current HBM4 base dies and moving toward 3 nanometers for later products, which indicates a gradual shift rather than a single switch.
Process choice also affects cost and capacity. Advanced nodes are expensive and in high demand, and the same TSMC lines serve many of the world's largest chip designers. Adding the base dies of three memory suppliers to that demand raises questions about allocation, pricing and lead times, which suppliers and Nvidia will have to manage carefully as volumes grow toward 2027.
8. What does this mean for the AI hardware supply chain?
For TSMC, the reported plan strengthens a central position in AI hardware. The company already manufactures Nvidia's processors, and it would now also sit beneath the memory stacks that feed them. That raises its importance to the supply chain, and it also raises the concentration risk, since a disruption at one foundry could affect both the processor and its memory.
For Nvidia, standardizing the base die and embedding its own controller gives it greater influence over how its memory behaves, no matter which company produced the DRAM. It reduces dependence on the design choices of individual suppliers and could make it easier to bring a second or third source online when demand is high.
For the memory makers, the effect is mixed. Using TSMC may improve performance and qualification with the largest customer, yet it also gives up a layer of control and shares more of the value chain with the foundry. Micron has said it expects better profitability, which suggests that at least some suppliers see the trade as favorable.
9. What to watch next
Three points will show how the plan develops. The first is whether Micron meets its 2027 target for volume production of TSMC-made base dies. The second is how much HBM work Samsung keeps in-house and how much it routes to TSMC. The third is whether NVHBM reaches its goals of 30 percent more bandwidth and 15 percent lower power, which remain design targets until products ship.
Because the report relies on unnamed industry sources and none of the companies are quoted, details such as process nodes and timing could change. Readers should treat the specifics as provisional until Nvidia, TSMC or the memory makers confirm them, and watch for supplier earnings calls and product announcements as the next sources of firm information.
Analysts will also look for any sign of how Nvidia's competitors respond. Other accelerator makers use their own memory designs, and a successful standard from the market leader could influence the choices of memory suppliers, foundries and rival chip designers over the next product cycles. The scale of Nvidia's orders gives its specifications unusual weight across the industry, and suppliers rarely ignore them.